The present invention relates to semiconductor device fabrication, and in particular, to elevated source/drain (ESD) semiconductor devices.
As semiconductor devices continue to be scaled down, various methods have been relied upon for preserving the channel length. A minimum channel length (Lmin) may be determined, which indicates the minimum length at which a channel may be formed before observing short-channel effects in the semiconductor device. The junction depth of the semiconductor device affects the minimum channel length. Thus, reducing the junction depth may allow for reducing the channel length while mitigating short-channel effects. However, reducing the junction depth may lead to an increase in intrinsic parasitic series resistances and undesirable junction leakage currents.
Conventional methods have relied upon elevating the source/drain regions to counter the effects that occur when reducing the junction depths. The elevated source/drain regions are typically formed by selectively growing an epitaxial (epi) structure over the source and drain regions. The epi structure forms an effective junction depth that is reduced according to the extent of the elevation without realizing an increase of intrinsic parasitic series resistances and undesirable junction leakage currents.
When fabricating semiconductor devices having two different doped channel regions (e.g., a p-type doped channel region and an n-type doped channel region) on a common substrate layer, separate epi growth processes (i.e., a dual epi process) must be used. The dual epi process, however, forms spacers on a first gate stack (a p-type semiconductor gate stack) having a greater thickness than spacers on a second gate stack (an n-type semiconductor gate stack). The thicker spacers cause the corresponding epi structure (i.e., the elevated S/D region) to be formed further away from the gate stack. The increased distance (i.e., the effective S/D distance) between the elevated S/D region and the corresponding gate stack inhibits doped ions of the epi structures from diffusing beneath the gate stack.